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FEATURES Programmable Charge Current High Precision Battery Voltage Limit Precision 2.000 V Reference Low Voltage Drop Current Sense: 300 mV Full Scale Full Operation in Shorted and Open Battery Conditions Drives Diode-Side of Optocoupler Wide Operating Supply Range: 2.7 V to 16 V Undervoltage Lockout SO-8 Package ADP3810 Internal Precision Voltage Divider for Battery Sense Four Final Battery Voltage Options Available: 4.2 V, 8.4 V, 12.6 V, 16.8 V ADP3811 Adjustable Final Battery Voltage APPLICATIONS Battery Charger Controller for: LiIon Batteries (ADP3810) NiCad, NiMH Batteries (ADP3811) GENERAL DESCRIPTION
Secondary Side, Off-Line Battery Charger Controllers ADP3810/ADP3811
off-line applications, the output directly drives the diode side of an optocoupler to give isolated feedback control of a primary side PWM. The circuitry includes two gain (gm) stages, a precision 2.0 V reference, a control input buffer, an Undervoltage Lock Out (UVLO) comparator, an output buffer and an overvoltage comparator. The current limit amplifier senses the voltage drop across an external sense resistor to control the average current for charging a battery. The voltage drop can be adjusted from 25 mV to 300 mV, giving a charging current limit from 100 mA to 1.2 amps with a 0.25 sense resistor. An external dc voltage on the VCTRL input sets the voltage drop. Because this input is high impedance, a filtered PWM output can be used to set the voltage. As the battery voltage approaches its voltage limit, the voltage sense amplifier takes over to maintain a constant battery voltage. The two amplifiers essentially operate in an "OR" fashion. Either the current is limited, or the voltage is limited. The ADP3810 has internal thin-film resistors that are trimmed to provide a precise final voltage for LiIon batteries. Four voltage options are available, corresponding to 1-4 LiIon cells as follows: 4.2 V, 8.4 V, 12.6 V and 16.8 V. The ADP3811 omits these resistors allowing any battery voltage to be programmed with external resistors.
The ADP3810 and ADP3811 combine a programmable current limit with a battery voltage limit to provide a constant current, constant voltage battery charger controller. In secondary side,
FUNCTIONAL BLOCK DIAGRAM
GND VCS VCC VREF VSENSE
1.5M VREF
80k
UVLO VREF UVLO
R1 R2
ADP3810 ONLY
VCTRL UVLO GM1
ADP3810/ ADP3811
GM2
GM
COMP
OUT
REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 (c) Analog Devices, Inc., 1996
ADP3810/ADP3811-SPECIFICATIONS (-40 C T +85 C, V
A
CC
= 10.0 V, unless otherwise noted)
ADP3810 Typ Max -300 -25 86 10 -285 -18 1.2 40 +1.0 210k 420k 630k 840k Units mV mV V dB nA % mV nA dB V +1.0 +1.8 +0.25 0.02 % % % %/V V p-p mA mA V V/V V V V mA mA
Parameter CURRENT SENSE1 Full-Scale Current Sense Voltage Minimum Current Sense Voltage Current Programming Input Range Gain (VOUT/VCS) Control Input Bias Current VOLTAGE SENSE Accuracy2--ADP3810 Input Resistance--ADP3810 Input Resistance--ADP3810 Input Resistance--ADP3810 Input Resistance--ADP3810 Offset Voltage--ADP3811 Bias Current--ADP3811 Gain (VOUT/VSENSE)3 REFERENCE Output Voltage Accuracy ADP3810 ADP3811 Load Regulation Line Regulation Output Voltage Noise Load Current (Sourcing) OUTPUT Output Current Saturation Voltage Gain (VOUT/VCOMP) UNDERVOLTAGE LOCKOUT Trip Point-On Trip Point-Off POWER SUPPLY Operating Range Quiescent Current Turn-Off Current OVERVOLTAGE COMPARATOR Threshold ADP3810 ADP3811 Response Time
Conditions VCTRL = 1.2 V 0.0 V VCTRL 0.1 V RL = 1 k VCTRL Pin
Symbol
Min -315 -32 0.0 74
VCTRL AVCS IBCTRL
-1.0 4.2 V Option 8.4 V Option 12.6 V Option 16.8 V Option RIN RIN RIN RIN VOS IB AVBAT VREF -1.0 -1.8 -0.25 eN IL IOUT VSAT AVOUT 0.004 35 10 6 0.1 6 2.65 2.6
-2.5 60 1 74 2.000
+2.5 10
RL = 1 k CL = 0.1 F4
ILOAD = 0 mA to 5 mA VCC = 2.7 V to 16 V 0.1 Hz to 10 Hz
5 4
VCC = 2.7 V IOUT = 4 mA, VCC-VOUT RL = 1 k
0.4
2.7
2.5 2.7 IQ
VCC 2.7 V VCC 2.5 V
1.5 0.5
16 3 1
Percent Above Full Scale5 Percent Above Full Scale5 IOUT from 0 mA to 2 mA
VOV% VOV% tr
6 6 8
% % s
NOTES 1 20 k resistor from current sense voltage to V CS pin. 2 Applies to 4.2 V, 8.4 V, 12.6 V and 16.8 V options. Includes all error from offset voltage, bias current, resistor divider and voltage reference. 3 Does not include attenuation of input resistor divider for ADP3810. 4 0.1 F load capacitor required for reference operation. 5 Full scale is the programmed final battery voltage: 4.2 V, 8.4 V, 12.6 V or 16.8 V for the ADP3810 or 2.0 V at V SENSE for the ADP3811. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. Specifications subject to change without notice.
-2-
REV. 0
ADP3810/ADP3811
ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION
VSENSE 1 VCS 2 COMP 3 8 VCC
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . -0.4 V to 18 V VCTRL, VCS Input Range . . . . . . . . . . . . . . . . . . -0.4 V to VCC VSENSE Input Range (ADP3811) . . . . . . . . . . . . -0.4 V to VCC VSENSE Input Range (ADP3810) . . . . . . . . . . . -0.4 V to 20 V Maximum Power Dissipation . . . . . . . . . . . . . . . . . . 500 mW Operating Temperature Range . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . . -65C to 150C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300C
ORDERING GUIDE
ADP3810 ADP3811
7 VREF
TOP VIEW 6 GND (Not to Scale) 5 VCTRL OUT 4
PIN DESCRIPTION
Mnemonic Function
Model ADP3810AR-4.2 ADP3810AR-8.4 ADP3810AR-12.6 ADP3810AR-16.8 ADP3811AR
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Option SO-8 SO-8 SO-8 SO-8 SO-8
Battery Voltage 4.2 V 8.4 V 12.6 V 16.8 V Adjustable
VSENSE VCS VREF COMP OUT VCTRL VCC GND
Battery Voltage Sense Input. Current Sense Input. Reference Output. Nominally 2.0 V. External Compensation Pin. Optocoupler Current Output Drive. DC Control Input to Set Current Limit, 0 V to 1.2 V. Positive Supply. Ground Pin.
VBAT OUT VIN IN CTRL DC/DC CONVERTER GND 2.0V R3 R1 0.1F 0.1F R2 ADP3811 ONLY ICHARGE RETURN VRCS RCS BATTERY
VCS VREF 1.5M VCTRL 80k
VCC UVLO UVLO
VREF
VSENSE R1 ADP3810 ONLY R2
GM1 BUFFER
ADP3810/ ADP3811
200
VREF GM2
UVLO IOUT OUT GM3 1.2V 100A
COMP CC RC
GND
Figure 1. Simplified Battery Charger
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3810/ADP3811 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
-3-
ADP3810/ADP3811-Typical Performance Characteristics
2 TYPICAL PARTS
REFERENCE VOLTAGE - Volts
DROPOUT VOLTAGE - mV
2.002
VCC = +10V I L = 100A C L = 0.1F
VCC = +10V C L = 0.1F 200
REFERENCE DROPOUT VOLTAGE - Volts
2.004
250
0.14 VCC = +10V I L = 5mA C L = 0.1F
0.12
2.000
150
0.10
1.998
100
0.08
1.996
50
0.06
1.994 -50
0
-25
0 25 50 TEMPERATURE - C
75
100
0
3
6 9 12 LOAD CURRENT - mA
15
18
0.04 -50
-25
0 25 50 TEMPERATURE - C
75
100
Figure 2. Reference Output Voltage vs. Temperature for Two Typical Parts
Figure 3. Reference Drop-Out Volt age (VCC-VREF) vs. Load Current
Figure 4. Reference Dropout Voltage vs. Temperature
-20
REFERENCE NOISE DENSITY - nV/Hz
3000
1.6
CHARGE CURRENT - Amps
-30
VCC = +10V I L = 100A C L = 0.1F
2500
VCC = +10V I L = 100A C L = 0.1F
1.4 1.2 1.0 0.8 0.6 0.4 0.2 0
RCS = 0.25 R3 = 20k
-40 PSRR - dB
2000
-50
1500
-60
1000
-70 -80 100
500 0
1k
10k 100k FREQUENCY - Hz
1M
1
10
100 1k FREQUENCY - Hz
10k
0
0.2 0.4 0.6 0.8 1.0 1.2 CONTROL VOLTAGE, VCTRL - Volts
1.4
Figure 5. Reference PSRR vs. Frequency
Figure 6. Reference Noise Density vs. Frequency
Figure 7. Charge Current vs. Control Voltage
-294
-294
100
CURRENT SENSE VOLTAGE - mV
CURRENT SENSE VOLTAGE - mV
VCC = +10V R3 = 20k -296
VCC = +10V R3 = 20k -296
OPEN-LOOP GAIN - dB
80 60 40 20 0 -20 -40 PHASE GAIN
C COMP = 0.01F TA = +25C VCC = +10V
45 90 135 180 225 1M
-300
-300
-302
-302
-304 -50
-304 -25 0 25 50 TEMPERATURE - C 75 100
2
6 8 10 12 14 4 SUPPLY VOLTAGE, VCC - Volts
16
-60 10
100
1k 10k 100k FREQUENCY - Hz
Figure 8. Full-Scale Current Sense Voltage vs. Temperature
Figure 9. Full-Scale Current Sense Voltage vs. VCC
Figure 10. GM1 Open-Loop Gain and Phase vs. Frequency
-4-
REV. 0
PHASE SHIFT - Degrees
-298
-298
0
ADP3810/ADP3811
100
VOLTAGE SENSE ACCURACY - %
GAIN
VOLTAGE SENSE ACCURACY - %
80
OPEN-LOOP GAIN - dB
60 40 20 0 -20 -40 -60 10 PHASE
C COMP = 0.01F TA = +25C VCC = +10V
1.0 VCC = +10V 0.5
1.0 TA = +25C 0.5
0 45 90 135 180 225 1M
PHASE SHIFT - Degrees
0
0
-0.5
-0.5
-1.0
-1.0
100
1k 10k 100k FREQUENCY - Hz
-1.5 -50
-1.5
-25
0 25 50 TEMPERATURE - C
75
100
0
6 9 12 15 3 SUPPLY VOLTAGE, VCC - Volts
18
Figure 11. GM2 Open-Loop Gain and Phase vs. Frequency
Figure 12. ADP3810 Voltage Sense Accuracy vs. Temperature
Figure 13. ADP3810 Voltage Sense Accuracy vs. VCC
1.0 VCC = +10V 0.5
GM2 OFFSET - mV
1.0 TA = +25C
2.5 VCC = +10V
0
0
VSENSE BIAS CURRENT - nA
0 6 9 12 15 3 SUPPLY VOLTAGE, VCC - Volts 18
0.5
2.0
GM2 OFFSET - mV
1.5
-0.5
-0.5
1.0
-1.0
-1.0
0.5
-1.5 -50
-25
0 25 50 TEMPERATURE - C
75
100
-1.5
0 -50
-25
0 25 50 TEMPERATURE - C
75
100
Figure 14. ADP3811 GM2 Offset vs. Temperature
Figure 15. ADP3811, GM2 Offset vs. VCC
Figure 16. ADP3811 VSENSE Bias Current vs. Temperature
2.5 TA = +25C
VSENSE BIAS CURRENT - nA
120 VCC = +10V T A = +25C
12 VCC = +10V 10
2.0
100
QUANTITY - Parts
80
60
1.0
VOV% - %
1.5
8
6
40 4
0.5
20 0 5.0 5.2 5.4 5.6 5.8 6.0 6.2 6.4 6.6 6.8 7.0 VOV% - %
0
0
6 9 12 15 3 SUPPLY VOLTAGE, VCC - Volts
18
2 -50
-25
0 25 50 TEMPERATURE - C
75
100
Figure 17. ADP3811 VSENSE Bias Current vs. VCC
Figure 18. Overvoltage Comparator Distribution (VOV%)
Figure 19. Overvoltage Comparator Threshold (VOV%) vs. Temperature
REV. 0
-5-
ADP3810/ADP3811
240 VCC = +10V T A = +25C R L = 1k
8 RL = 1k VOUT = +1.0V
VOUT/VCOMP - V/V
0.25 VCC = +10V I LOAD = 5mA
200
TA = -40C 6 TA = +25C 5 TA = +85C
160
OUTPUT SATURATION VOLTAGE, VSAT - Volts
7
0.20
QUANTITY - Parts
0.15
120
0.10
80
40 0 5.0 5.2 5.4 5.6 5.8 6.0 6.2 6.4 6.6 6.8 7.0 OUTPUT GAIN (VOUT/VCOMP) - V/V
4
0.05
3
0
3
6
9 12 VCC - Volts
15
18
0 -50
-25
0 25 50 TEMPERATURE - C
75
100
Figure 20. Output Gain (VOUT/VCOMP) Distribution
Figure 21. Output Gain (VOUT/VCOMP) vs. VCC
Figure 22. VSAT vs. Temperature
APPLICATIONS SECTION Functional Description
Description of Battery Charging Operation
The ADP3810 and ADP3811 are designed for charging NiCad, NiMH and LiIon batteries. Both parts provide accurate voltage sense and current sense circuitry to control the charge current and final battery voltage. Figure 1 shows a simplified battery charging circuit with the ADP3810/ADP3811 controlling an external dc-dc converter. The converter can be one of many different types such as a Buck converter, Flyback converter or a linear regulator. In all cases, the ADP3810/ADP3811 maintains accurate control of the current and voltage loops, enabling the use of a low cost, industry standard dc-dc converter without compromising system performance. Detailed realizations of complete circuits including the dc-dc converter are included later in this data sheet. The ADP3810 and ADP3811 contain the following blocks (shown in Figure 1): * Two "GM" type error amplifiers control the current loop (GM1) and the voltage loop (GM2). * A common COMP node is shared by both GM amplifiers such that an RC network at this node helps compensate both control loops. * A precision 2.0 V reference is used internally and is available externally for use by other circuitry. The 0.1 F bypass capacitor shown is required for stability. * A current limited buffer stage (GM3) provides a current output, IOUT, to control an external dc-dc converter. This output can directly drive an optocoupler in isolated converter applications. The dc-dc converter must have a control scheme such that higher IOUT results in lower duty cycle. If this is not the case, a simple, single transistor inverter can be used for control phase inversion. * An amplifier buffers the charge current programming voltage, VCTRL, to provide a high impedance input. * An UVLO circuit shuts down the GM amplifiers and the output when the supply voltage (VCC) falls below 2.7 V. This protects the charging system from indeterminate operation. * A transient overshoot comparator quickly increases IOUT when the voltage on the "+" input of GM2 rises over 120 mV above VREF. This clamp shuts down the dc-dc converter to quickly recover from overvoltage transients and protect external circuitry. -6-
The IC based system shown in Figure 1 charges a battery with a dc current supplied by a dc-dc converter, which is most likely a switching type supply but could also be a linear supply where feasible. The value of the charge current is controlled by the feedback loop comprised of RCS, R3, GM1, the external dc-dc converter and a dc voltage at the VCTRL input. The actual charge current is set by the voltage, VCTRL, and is dependent upon the choice for the values of RCS and R3 according to the formula below:
I CHARGE = 1 R3 x xV CTRL RCS 80 k
Typical values are RCS = 0.25 and R3 = 20 k, which result in a charge current of 1.0 A for a control voltage of 1.0 V. The 80 k resistor is internal to the IC, and it is trimmed to its absolute value. The positive input of GM1 is referenced to ground, forcing the VCS pin to a virtual ground. The resistor RCS converts the charge current into the voltage at VRCS, and it is this voltage that GM1 is regulating. The voltage at VRCS is equal to -(R3/80 k) VCTRL. When VCTRL equals 1.0 V, VRCS equals -250 mV. If VRCS falls below its programmed level (i.e., the charge current increases), the negative input of GM1 goes slightly below ground. This causes the output of GM1 to source more current and drive the COMP node high, which forces the current, IOUT, to increase. A higher IOUT decreases the drive to the dc-dc converter, reducing the charging current and balancing the feedback loop. As the battery approaches its final charge voltage, the voltage loop takes over. The system becomes a voltage source, floating the battery at constant voltage thereby preventing overcharging. The constant voltage feature also protects the circuitry that is actually powered by the battery from overvoltage if the battery is removed. The voltage loop is comprised of R1, R2, GM2 and the dc-dc converter. The final battery voltage is simply set by the ratio of R1 and R2 according to the following equation (VREF = 2.000 V):
R1 V BAT = 2.000V x +1 R2
If the battery voltage rises above its programmed voltage, VSENSE is pulled above VREF. This causes GM2 to source more current, raising the COMP node voltage and IOUT. As with the REV. 0
ADP3810/ADP3811
current loop, the higher IOUT reduces the duty cycle of the dc-dc converter and causes the battery voltage to fall, balancing the feedback loop. Each GM stage is designed to be asymmetrical so that each amplifier can only source current. The outputs are tied together at the COMP node and loaded with an internal constant current sink of approximately 100 A. Whichever amplifier sources more current controls the voltage at the COMP node and therefore controls the feedback. This scheme is a realization of an analog "OR" function where GM1 or GM2 has control of the dc-dc converter and the charging circuitry. Whenever the circuit is in full current limiting or full voltage limiting, the respective GM stage sources an identical amount of current to the fixed current sink. The other GM stage sources zero current and is out of the loop. In the transition region, both GM stages source some of the current to comprise the full amount of the current sink. The high gains of GM1 and GM2 ensure a smooth but sharp transition from current control to voltage control. Figure 24 shows a graph of the transition from current to voltage mode, that was measured on the circuit in Figure 23 as detailed below. Notice that the current stays at its full programmed level until the battery is within 200 mV of the final programmed voltage (10 V in this case), which maintains fast charging through almost all of the battery voltage range. This improves the speed of charging compared to a scheme that reduces the current at lower battery voltages. The second element in a battery charging system is some form of a dc-dc converter. To achieve high efficiency, the dc-dc converter can be an isolated off-line switching power supply, or it can be an isolated or nonisolated Buck or other type of switching power supply. For lower efficiency requirements, a linear regulator fed from a wall adapter can be used. In the above discussion, the current, IOUT, controls the duty cycle of a switching supply; but in the case of the linear regulator, IOUT controls the pass transistor drive. Examples of these topologies are shown later in this data sheet. If an off-line supply such as a flyback converter is used, and isolation between the control logic and the ADP3810/ADP3811 is required, an optocoupler can be inserted between the ADP3810/ADP3811 output and the control input of the primary side PWM.
Charge Termination
program the VCTRL input to set the charge current. The high impedance of VCTRL enables the inclusion of an RC filter to integrate a PWM output into a dc control voltage.
Compensation
The voltage and current loops have significantly different natural and crossover frequencies in a battery charger application, so the two loops most likely need different pole/zero feedback compensation. Figure 1 shows a single RC network from the COMP node to ground. This is primarily for low frequency compensation (fC< 100 Hz) of the voltage loop. Since the COMP node is shared by both GM stages, this compensation also affects the current loop. The internal 200 resistor does change the zero location of the compensation for the current loop with respect to the voltage loop. To provide a separate higher frequency compensation (fC ~ 1 kHz-10 kHz), a second series RC may be needed. A detailed calculation of the compensation values is given later in this data sheet.
ADP3810 and ADP3811 Differences
The main difference between the ADP3810 and the ADP3811 is illustrated in Figure 1. The resistors R1 and R2 are external for the ADP3811 and internal for the ADP3810. The ADP3810 is specifically designed for LiIon battery charging, and thus, the internal resistors are precision thin-film resistors laser trimmed for LiIon cell voltages. Four different final voltage options are available in the ADP3810: 4.2 V, 8.4 V, 12.6 V, and 16.8 V. For slightly different voltages to accommodate different LiIon chemistries, please contact the factory. The ADP3811 does not include the internal resistors, allowing the designer to choose any final battery voltage by appropriately selecting the external resistors. Because the ADP3810 is specifically for LiIon batteries, the reference is trimmed to a tighter accuracy specification of 1% instead of 2% for the ADP3811.
VCTRL Input and Charge Current Programming Range
If the system is charging a LiIon battery, the main criteria to determine charge termination is the absolute battery voltage. The ADP3810, with its accurate reference and internal resistors, accomplishes this task. The ADP3810's guaranteed accuracy specification of 1% of the final battery voltage ensures that a LiIon battery will not be overcharged. This is especially important with LiIon batteries because overcharging can lead to catastrophic failure. It is also important to insure that the battery be charged to a voltage equal to its optimal final voltage (typically 4.2 V per cell). Stopping at less than 1% of full-scale results in a battery that has not been charged to its full mAh capacity, reducing the battery's run time and the end equipment's operating time. The ADP3810/ADP3811 does not include circuitry to detect charge termination criteria such as -V/t or T/t, which are common for NiCad and NiMH batteries. If such charge termination schemes are required, a low cost microcontroller can be added to the system to monitor the battery voltage and temperature. A PWM output from the microcontroller can subsequently REV. 0
The voltage on the VCTRL input determines the charge current level. This input is buffered by an internal single supply amplifier (labeled BUFFER) to allow easy programmability of VCTRL. For example, for a fixed charge current, VCTRL can be set by a resistor divider from the reference output. If a microcontroller is setting the charge current, a simple RC filter on VCTRL enables the voltage to be set by a PWM output from the micro. Of course, a digital-to-analog converter could also be used, but the high impedance input makes a PWM output the economical choice. The bias current of VCTRL is typically 25 nA, which flows out of the pin. The guaranteed input voltage range of the buffer is from 0.0 V to 1.2 V. When VCTRL is in the range of 0.0 V to 0.1 V, the output of the internal amplifier is fixed at 0.1 V. This corresponds to a charge current of 100 mA for RCS = 0.25 , R3 = 20 k. The graph of charge current versus VCTRL in Figure 7 shows this relationship. Figure 1 shows a diode in series with the buffer's output and a 1.5 M resistor from VREF to this output. The diode prevents the amplifier from sinking current, so for small input voltages the buffer has an open output. The 1.5 M resistor forms a divider with the internal 80 k resistor to fix the output at 0.1 V, i.e., about 10% of the maximum current. This corresponds to the typical trickle charge current level for NiCad batteries. When VCTRL rises above 0.1 V, the buffer sources current and the output follows the input. The total range of VCTRL from 0.0 V. to 1.2 V results in a charge current range from 100 mA to 1.2 A (for RCS = 0.25 , R3 = 20 k). Larger -7-
ADP3810/ADP3811
charge current levels can be obtained by either reducing the value of RCS or increasing the value of R3. The main penalty of increasing R3 is lower efficiency due to the larger voltage drop across RCS, and the penalty of decreasing RCS is lower accuracy (but higher efficiency) as discussed below.
VREF Output
The internal band gap reference is not only used internally for the voltage and current loops, but it is also available externally if an accurate voltage is needed. The reference employs a pnp output transistor for low dropout operation. Figure 3 shows a typical graph of dropout voltage versus load current. The reference is guaranteed to source 5 mA with a dropout voltage of 400 mV or less. The 0.1 F capacitor on the reference pin is integral in the compensation of the reference and is therefore required for stable operation. If desired, a larger value of capacitance can also be used for the application, but a smaller value should not be used. This capacitor should be located close to the VREF pin. Additional reference performance graphs are shown in Figures 2 through 6.
Output Stage
the ADP3810 is specified with respect to the final battery voltage. This is tested in a full feedback loop so that the single accuracy specification given in the specification table accounts for all of the errors mentioned above. For the ADP3811, the resistors are external, so the final voltage accuracy needs to be determined by the designer. Certainly, the tolerance of the resistors has a large impact on the final voltage accuracy, and 1% or better is recommended.
Supply Range
The output stage performs two important functions. It is a buffer for the compensation node, and as such, it has a high impedance input. It is also a GM stage. The OUT pin is a current output to enable the direct drive of an optocoupler for isolated applications. The gain from the COMP node to the OUT pin is approximately 5 mA/V. With a load resistor of 1 k, the voltage gain is equal to five as specified in the data sheet. A different load resistor results in a gain equal to RL x (5 mA/V). Figures 20 and 21 show how the gain varies from part to part and versus the supply voltage, respectively. The guaranteed output current is 5 mA, which is much more than the typical 1 mA to 2 mA required in most applications.
Current Loop Accuracy Considerations
The supply range is specified from 2.7 V to 16 V. However, a final battery voltage option for the ADP3810 is 16.8 V. The 16.8 V is divided down by the thin film resistors to 2.0 V internally. Thus, the input to GM2 never sees much more than 2.0 V, which is well below the VCC voltage limit. In fact, VCC can be fixed to 2.7 V and the ADP3810 will still control the charging of a 16.8 V battery stack. The ADP3811, with external resistors, can charge batteries to voltages well in excess of its supply voltage. However, if the final battery voltage is above 16 V, VCC cannot be supplied directly from the battery as it is in Figure 1. Alternative circuits must be employed as will be discussed later. Decoupling capacitors should be located close to the supply pin. The actual value of the capacitors depends on the application, but at the very least a 0.1 F capacitor should be used.
OFF-LINE, ISOLATED, FLYBACK BATTERY CHARGER
The accuracy of the current loop is dependent on several factors such as the offset of GM1, the offset of the VCTRL buffer, the ratio of the internal 80 k compared to the external 20 k resistor, and the accuracy of RCS. The specification for current loop accuracy states that the full-scale current sense voltage, VRCS, of -300 mV is guaranteed to be within 15 mV of this value. This assumes an exact 20 k resistor for R3. Any errors in this resistor will result in further errors in the charge current value. For example, a 5% error in resistor value will add a 5% error to the charge current. The same is true for RCS, the current sense resistor. Thus, 1% or better resistors are recommended. As mentioned above, decreasing the value of RCS increases the charge current. Since it is VRCS that is specified, the actual value of RCS is not accounted for in the specification. An example where RCS = 0.1 illustrates its impact on the accuracy of the charge current. The range of VRCS is from -25 mV 5 mV to -300 mV 15 mV. This results in a charge current range from 250 mA 50 mA to 3 A 150 mA, as opposed to a charge current range of 100 mA 20 mA to 1.2 A 60 mA for RCS = 0.25 . Thus, not only is the minimum current changed, but the absolute variation around the set point is increased (although the percentage variation is the same).
Voltage Loop Accuracy Considerations
The ADP3810 and ADP3811 are ideal for use in isolated chargers. Because the output stage can directly drive an optocoupler, feedback of the control signal across an isolation barrier is a simple task. Figure 23 shows a complete flyback battery charger with isolation provided by the flyback transformer and the optocoupler. The essential operation of the circuit is not much different from the simplified circuit described in Figure 1. The GM1 loop controls the charge current, and the GM2 loop controls the final battery voltage. The dc-dc converter block is comprised of a primary side PWM circuit and flyback transformer, and the control signal passes through the optocoupler. The circuit in Figure 23 incorporates all of the features necessary to assure long battery life with rapid charging capability. By using the ADP3810 for charging LiIon batteries, or the ADP3811 for NiCad and NiMH batteries, component count is minimized, reducing system cost and complexity. With the circuit as presented or with its many possible variations, designers no longer need to compromise charging performance and battery life to achieve a cost effective system.
Primary Side Considerations
A typical current-mode flyback PWM controller was chosen for the primary control circuit for several reasons. First and most importantly, it is capable of operating from very small duty cycles to near the maximum designed duty cycle. This makes it a good choice for a wide input ac supply voltage variation requirement, which is usually between 70 V-270 V ac for world wide applications. Add to that the additional requirement of 0% to 100% current control, and the PWM duty cycle must have a wide range. This charger achieves these ranges while maintaining stable feedback loops. The detailed operation and design of the primary side PWM is widely described in the technical literature and is not detailed here. However, the following explanation should make clear the reasons for the primary side component choices. The PWM frequency is set to around 100 kHz as a reasonable compromise -8- REV. 0
The accuracy of the voltage loop is dependent on the offset of GM2, the accuracy of the reference voltage, the bias current of GM2 through R1 and R2, and the ratio of R1/R2. For the demanding application of charging LiIon batteries, the accuracy of
ADP3810/ADP3811
10nF 1N4148 100 22F 50F/450V TX1** 9.1 3W L AC 120/220V- N 330pF 330 VCC RF 3.3k 3.3k CF 1nF COMP VFB OUTPUT 10k 0.1F 0.1F 1k ISENSE 470pF VREF RT/CT * 1% TOLERANCE ** TX1 f = 120kHz LPR = 750H LSEC = 7.5H 3.3k 2.2nF CC1 1F RC1 10k OPTO COUPLER MOC8103 GND 0.1F OUT 1.6 VCS VREF VCC VSENSE VCTRL GND 0.1F CHARGE CURRENT CONTROL VOLTAGE CC2 0.2F 10 IRFBC30 RC2 300 MAXIMUM VOUT = +10V CHARGE CURRENT 0.1A TO 1A 1A 13V 47F 100k 1N4148 22nF MURD320 R3 20k* CF1 1mF R4 1.2k R1 80.6k* R2 20k* 3.3V CF2 220F VOUT BATTERY
RCS 0.25*
PWM 3845
ADP3810/ADP3811
COMP
Figure 23. ADP3810/ADP3811 Controlling an Off-Line, Flyback Battery Charger
between inductive and capacitive component sizes, switching losses and cost. The primary PWM-IC circuit derives its starting VCC through a 100 k resistor directly from the rectified ac input. After startup, a conventional bootstrapped sourcing circuit from an auxiliary flyback winding wouldn't work, since the flyback voltage would be reduced below the minimum VCC level specified for the 3845 under a shorted or discharged battery condition. Therefore, a voltage doubler circuit was developed (as shown in Figure 23) that provides the minimum required VCC for the IC across the specified ac voltage range even with a shorted battery. While the signal from the ADP3810/ADP3811 controls the average charge current, the primary side should have a cycle by cycle limit of the switching current. This current limit has to be designed so that, with a failed or malfunctioning secondary circuit or optocoupler, the primary power circuit components (the FET and transformer) won't be overstressed. In addition, during start-up or for a shorted battery, VCC to the ADP3810/ ADP3811 won't be present. Thus, the primary side current limit is the only control of the charge current. As the secondary side VCC rises above 2.7 V, the ADP3810/ADP3811 takes over and controls the average current. The primary side current limit is set by the 1.6 current sense resistor connected between the power NMOS transistor, IRFBC30, and ground. The current drive of the ADP3810/ADP3811's output stage directly connects to the photodiode of an optocoupler with no additional circuitry. With 5 mA of output current, the output stage can drive a variety of optocouplers. An MOC8103 is shown as an example. The current of the photo-transistor flows through the 3.3 k feedback resistor, RFB, setting the voltage at the 3845's COMP pin, thus controlling the PWM duty cycle. The controlled switching regulator should be designed as shown so that more LED current from the optocoupler reduces the duty cycle of the converter. Approximately 1 mA should be the REV. 0
maximum current needed to reduce the duty cycle to zero. The difference between the 5 mA drive and the 1 mA requirement leaves ample margin for variations in the optocoupler gain.
Secondary Side Considerations
For the lowest cost, a current-mode flyback converter topology is used. Only a single diode is needed for rectification (MURD320 in Figure 23), and no filter inductor is required. The diode also prevents the battery from back driving the charger when input power is disconnected. A 1 mF capacitor filters the transformer current, providing an average dc current to charge the battery. The resistor, RCS, senses the average current which is controlled via the VCS input. In this case, the charging current has high ripple due to the flyback architecture, so a low-pass filter (R3 and CC2) on the current sense signal is needed. This filter has an extra inverted zero due to RC2 to improve the phase margin of the loop. The 1 mF capacitor is connected between VOUT and the 0.25 sense resistor. To provide additional decoupling to ground, a 220 F capacitor is also connected to VOUT. Output ripple voltage is not critical, so the output capacitor was selected for lowest cost instead of lowest ripple. Most of the ripple current is shunted by the parallel battery, if connected. If needed, high frequency ringing caused by circuit parasitics can be damped with a small RC snubber across the rectifier. The VCC source to the ADP3810/ADP3811 can come from a direct connection to the battery as long as the battery voltage remains below the specified 16 V operating range. If the battery voltage is less then 2.7 V (e.g., with a shorted battery, or a battery discharged below it's minimum voltage), the ADP3810/ ADP3811 will be in Undervoltage Lock Out (UVLO) and will not drive the optocoupler. In this condition, the primary PWM circuit will run at its designed current limit. The VCC of the ADP3810/ADP3811 can be boosted using the circuit shown in Figure 23. This circuit keeps VCC above 2.7 V as long as the -9-
ADP3810/ADP3811
battery voltage is at least 1.5 V with a programmed charge current of 0.1 A. For a higher programmed charge current, the battery voltage can drop below 1.5 V, and VCC is still maintained above 2.7 V. This is because of the additional energy in the flyback transformer, which transfers more energy through the 10 nF capacitor to VCC. The 22 F bypass capacitor on VCC stores the energy transferred through the 10 nF capacitor.
Secondary Side Component Calculations Design Criteria:
The Battery Charge Current vs. Battery Voltage characteristics for four different charge current settings are given in Figure 24. The high gain of the internal amplifiers ensures the sharp transition between current mode and voltage mode regardless of the charge current setting. The fact that the current remains at full charging until the battery is very close to its final voltage ensures fast charging times. The transient performance for various turn-on and turn-off conditions is detailed in Figures 25, 26 and 27. Figure 25 shows the output voltage when power is applied with no battery connected. As shown, the output voltage quickly rises and overshoots its set voltage. The internal comparator responds to this and clamps the voltage giving a quick recovery. Without the internal comparator, an external zener would be required to clamp the voltage to the LED anode. Figure 26 shows the battery current when connecting and disconnecting a battery. The actual trace shown is the voltage across RCS, which is negative for current flowing into the battery. There is an overshoot when the battery is connected, but the loop quickly takes control and limits the average current to the programmed 0.75 A. When the battery is removed, the current quickly returns to zero. The solid band on the scope is due to the current rising and falling with the switching of the PWM. The time scale is too slow to show the detail of this. Figure 27 shows the output voltage when a battery stack charged to 6 V is connected and then disconnected. As expected, when the battery is connected, the voltage immediately goes to 6 V. When the battery is disconnected, the voltage returns to the programmed float voltage of 10 V. Again, a small overshoot is present that is clamped by the internal comparator.
TA = +25 C NO BATTERY VIN = 220VAC
Charging a 6 cell NiCad battery. Max Individual Cell Voltage: VCELLMAX = 1.67 V Max Battery Stack Voltage: VOMAX = 6 x 1.67 V = 10 V Max Charge Current: IOMAX = 1 A Max Control Voltage: VCTRL = 1 V (for IOMAX = 1 A) RS Fixed Value: RS = 20 k Pick a Value for R1: R1 = 80.6 k The voltage limit of 10 V is approximately 10% above the maximum fully charged voltage when -V/t termination is used. This limit gives a second level of protection without interfering with -V/t charge termination.
Component Value Calculations:
Current Sense Resistor: Battery Divider, R2:
RCS = VCTRL/(4 x IOMAX) = 1/(4 x 1) = 0.25 W, 1%, 0.5 W R2 = VREF x R1/(VOMAX-VREF) R2 = 2 x 80.6 k/(10 V-2 V) = 20.15 k, Pick 20.0 k
The final voltage and charge current accuracy is dependent upon the resistor tolerances. Choose appropriate tolerances for the desired accuracy. One percent accuracy is recommended.
Charger Performance Summary
The charger circuit properly executes the charging algorithm exhibiting stable operation regardless of battery conditions, including an open circuit load. The circuit can charge to other battery voltages by modifying only the battery voltage sense divider. As would be expected, circuit efficiency is best at high battery voltages. Replacing the output blocking rectifier diode with a Schottky would improve efficiency if the Schottky's leakage could be tolerated, and its reverse voltage rating met the application requirement.
1.0 VCTRL = 1.0V 0.9 0.8 0.7 0.6 ILIMIT 0.5 0.4 0.3 0.2 0.1 0.0 2 3 4 5 6 VOUT 7 8 9 10 11 VCTRL = 0.25V VCTRL = 0.125V VCTRL = 0.5V
100 90
10V
10 0%
2V/DIV
0V
0.1sec/DIV
Figure 25. Flyback Charger Output Voltage Transient at Power Turn On, No Battery Attached
0.0V
100
-200mV
90
TA = +25 C VCTRL = 0.775V VIN = 220VAC
10 0%
0.2V/DIV
20msec/DIV
Figure 24. Charge Current vs. Battery Voltage at Four Settings for the Flyback Charger in Figure 23
Figure 26. Charge Current Transient Response to Battery Connect/Disconnect
-10-
REV. 0
ADP3810/ADP3811
100 90
10V
TA = +25 C VIN = 220VAC VCTRL = 1V
options could be used, or the ADP3811 could be substituted with external resistors for a user set voltage. Notice the two grounds in the circuit. One ground is for the high current return to the VIN source and the other ground for the ADP3810 circuitry. RCS separates the two grounds, and it is important to keep them separate as shown. The adjustable version of the ADP1148 is used in this circuit instead of a fixed output version. The output voltage is fed back into the VFB pin, which is set to regulate at VBAT MAX + 0.5 V. Doing so provides a secondary, higher voltage limit without interfering with normal circuit operation. The control output of the ADP3810 is connected through a 560 resistor to the SENSE+ input of the ADP1148. The current, IOUT, adjusts the dc level on the SENSE+ pin, which is added to the current ramp across RSENSE. Higher IOUT increases the voltage on SENSE+ and reduces the duty cycle of the 1148, giving negative feedback. The circuit as shown can quickly and safely charge LiIon batteries while maintaining high efficiency. The efficiency of the ADP1148 is only degraded slightly by the addition of the ADP3810 and external circuitry. The 1.5 mA of supply current lowers the overall efficiency by approximately 1%-2% for maximum output current. The 0.25 sense resistor further lowers the efficiency due to the I2 x RCS power loss at high output currents. See the efficiency discussion in the ADP1148 data sheet for more information.
Linear Regulator
6V
10 0%
2V/DIV
0V
50msec/DIV
Figure 27. Output Voltage Transient Response to Battery Connect/Disconnect
NONISOLATED TOPOLOGIES Buck Switching Regulators
The ADP3810/ADP3811 and the ADP1148 can be combined to create a high efficiency buck regulator battery charger as shown in Figure 28. The ADP1148 is a high efficiency, synchronous, step-down regulator that controls two external MOSFETs as shown. Similar to the previous flyback circuit, the ADP3810 controls the average charge current and the final battery voltage, and the ADP1148 controls the cycle by cycle current. The following discussion explains the functionality of the circuit but does not go into detail on the ADP1148. For more information, the ADP1148 data sheet details the operation of the device and gives formulas for choosing the external components. The resistor RSENSE sets the cycle by cycle current limit to 1.5 A, which is far enough above the 1 A average current of the ADP3810 loop to avoid interfering but still provides a safe maximum current to protect the external components. The ADP3810 uses a 0.25 resistor, RCS, to sense the battery current. As before, a 20 k resistor is needed between RCS and the VCS input of the ADP3810. The RC network from VCS to ground performs the dual function of filtering and compensation. The voltage loop directly senses the battery voltage. Since the ADP3810 is used in this circuit instead of the ADP3811, VSENSE is connected directly to the battery. The internal resistors set the battery voltage to 8.4 V in this case. Of course, other voltage
A third charging circuit is shown in Figure 29. In this case, the switching supply is replaced with a linear regulator. The ADP3811 drives the gate of an N-channel MOSFET using an external 2N3904. As before, the ADP3811 senses the charge current through a 0.25 resistor. When the current increases above the limit, the internal GM amplifier causes the output to go high. This puts more voltage across R8, increasing the current in Q1. As the current increases, the gate of M1 is pulled lower, reducing the gate to source voltage and decreasing the charge current to complete the feedback loop. Because the ADP3811 has a current output, an external 1 k resistor is needed from the OUT pin to ground in order to convert the current to a voltage.
+VIN 0.1F 1F VIN
75k 560 P CH IRF7204 10 k
CIN 100F L* 62H RSENSE** 50 m
VCC VSENSE OUT VREF 0.1F VCTRL (0V TO 1V) 0.1F REF & CTRL RTN VIN RTN VCTRL GND COMP VREF 0V = NORMAL >1.5V = SHUTDOWN
P DRIVE VFB SHUTDOWN SENSE+ VCS RC2 560 CC2 220nF 20k CT CT 68pF S GND N DRIVE P GND
VBAT
100 1000pF BATTERY 100 COUT 220F D1 10BQ040 RCS 0.25
ADP3810
ADP1148
SENSE-
N CH IRF7403
RC1 2k CC1 1F
* COILTRONICS CTX-68-4 ** KRL SL-1-C1-0R068J
Figure 28. High Efficiency Buck Battery Charger
REV. 0
-11-
ADP3810/ADP3811
VBAT IRF7201 0.1F R1 80.6k VSENSE VREF 0.1F VCTRL R2 20k VCTRL & VREF RTN 0.1F VCTRL GND COMP VREF VCC OUT VCS RC2 560 CC2 220nF 220F R8 1k R1 VBAT = 2.0V ( -- + 1) R2 1k BATTERY 2N3904 250 1F 10k +VIN
ADP3811
RC1 200 0.25* CC1 1F 20k*
VIN RTN
Figure 29. ADP3811 Controlling a Linear Battery Charger
The trade-off between using a linear regulator as shown versus using a flyback or buck type of charger is efficiency versus simplicity. The linear charger in Figure 29 is very simple, and it uses a minimal amount of external components. However, the efficiency is poor, especially when there is a large delta between the input output voltages. The power loss in the pass transistor is equal to (VIN-VBAT) x ICHARGE. Since the circuit is powered from a wall adapter, efficiency may not be a big concern, but the heat dissipated in the pass transistor could be excessive. An important specification for this circuit is the dropout voltage, which is the difference between the input and output voltage at full charge current. There must be enough voltage to keep the N-channel MOSFET on. In this case, the dropout voltage is approximately 2.2 V for a 0.5 A output current. Two alternative
IRF7205 VIN 10k 10k ADP3811 VREF 2N3904 ADP3811 OUT 1k ADP3811 OUT 250 2N3904 VBAT VIN 2N3904 1k 2N5058 VBAT
charger application, the two loops need different inverted zero feedback loop compensations that can be accomplished by two series RC networks. One provides the needed low frequency (typical fC < 100 Hz) compensation to the voltage loop, and the other provides a separate high frequency (fC ~ 1 kHz-10 kHz) compensation to the current loop. In addition, the current loop input requires a ripple reduction filter on the VCS pin to filter out switching noise. Instead of placing both RC networks on the COMP pin, the current loop network is placed between VCS and ground as shown in Figure 23 (CC2 and RC2). Thus, it performs two functions, ripple reduction and loop compensation.
Loop Stability Criteria for Battery Charger Applications
1. The voltage loop has to be stable when the battery is removed or floating. 2. The current loop has to be stable when the battery is being charged within its specified charge current range. 3. Both loops have to be stable within the specified input source voltage range.
Flyback Charger Compensation
a. P-Channel MOSFET b. NPN Darlington Figure 30. Alternative Pass Transistor for Linear Regulator
realizations of the pass element are shown in Figure 30. In case (a), the pass transistor is a P-channel MOSFET. This provides a lower dropout voltage so that VBAT can be within a few hundred millivolts of VIN. In case (b), a Darlington configuration of two npn transistors is used. The dropout voltage of this circuit is approximately 2 V for a 0.5 A charge current.
STABILIZATION OF FEEDBACK LOOPS
The ADP3810/ADP3811 uses two transconductance error amplifiers with "merged" output stages to create a shared compensation point (COMP) for both the current and voltage loops as explained previously. Since the voltage and current loops have significantly different natural crossover frequencies in a battery
Figure 31 shows a simplified form of a battery charger system based on the off-line flyback converter presented in Figure 23. With some modifications (no optocoupler, for example), this model can also be used for converters such as a Buck Converter (Figure 28) or a Linear Regulator (Figure 29). GM1 and GM2 are the internal GM amplifiers of the ADP3810/ADP3811, and GM3 is the buffered output stage that drives the optocoupler. The primary side in Figure 23 is represented here by the "Power Stage," which is modeled as GM4, a linear voltage controlled current source model of the flyback transformer and switch. The "Voltage Error Amplifier" block is the internal error amplifier of the 3845 PWM-IC (RF = 3.3 k in Figure 23), and it is followed by an internal resistor divider. The optocoupler is modeled as a current controlled current source as shown. Its output current develops a voltage, VX, across RF. The gain values of all the blocks are defined below. This linear model makes the calculation of compensation values a manageable task. It also has the great benefit of allowing the simulation of the ac response using a circuit simulator, such as PSpice or MicroCap. For computer modeling, the GM
-12-
REV. 0
ADP3810/ADP3811
GM4 VBAT R1 80.6k BATTERY R2 20k
POWER STAGE
CF1 1nF
R4 1.2k
RCS 0.25 CC2 RC2 300 0.2F
CF2 220F
VC R 2R VX AV2 = 0.33V/V COMP VCTRL 1.0V
R3 20k
80k
VCS
2.0V
VSENSE
RF 3.3k VFB +5V
CF 1nF
GM1 8.3mA/V
GM2 2.1mA/V
VOLTAGE ERROR AMPLIFIER
OUT GM3 6mA/V OPTO COUPLER ITXOC = 0.36mA/mA
R6 200
ADP3810/ ADP3811
R5 400k COMP RC1 CC1
Figure 31. Block Diagram of the Linearized Feedback Model
amplifiers are represented by voltage controlled current sources, the optocoupler by a current controlled current source, and the error amplifier by a voltage controlled voltage source.
Design Criteria
Charging a 6 cell NiCad battery. Max Battery Stack Voltage: VOMAX = 6 x 1.67 V = 10 V Max Charge Current: IOMAX = 1 A RS Fixed Value: RS = 20 k Pick a value for R1: R1 = 80.6 k Calculated Current Sense Resistor: RCS = 0.25 Calculated Voltage Sense Divider: R2 = 20 k Output Filter Cap: CF1 = 1 mF (ESR = 0.1 ) 2nd Filter Cap: CF2 = 200 F (ESR = 0.2 )
Gain of Each Block
of these stages is the value of GM times the load resistance. At the COMP pin, the internal load resistance, R5, is typically 400 k. The optocoupler gain is the typical value taken from the MOC8103 data sheet. The voltage error amplifier gain is due to the resistor divider internal to the 3845 only. VX is the output of the internal amplifier, as labeled in Figure 31. The actual op amp is assumed to have sufficient open-loop gain and bandwidth compared to the system bandwidth; as a result, it can be considered an ideal transimpedance amplifier. The pole created by the 1 nF capacitor in parallel with RF is high enough in frequency to not affect the compensation. The power stage gain equation is linearized based on primary side current mode control with the flyback transformer operating with discontinuous inductor current. IOMAX is the maximum change in output current, which is equal to IOMAX-IOMIN. Since the minimum current is 0.0 A, IOMAX = IOMAX = 1 A. The maximum change in control voltage is set by internal circuitry within the 3845 to VC = 1 V. The load resistor, RLOAD, is different for the voltage and current loop cases. For the voltage loop without the battery, the effective load is R4, but for the current loop, the effective load is RCS. In the current loop, the voltage limit has not been reached, so the maximum output voltage is equal to the maximum output current times the load resistor. Thus, the entire expression under the square root reduces to 1.0. Substituting these values into the general equation for the power stage yields the specific gain values shown for GM4. When calculating the loop gain for the voltage loop and the current loop, there are two main differences. First, GM2 applies only to the voltage loop, and GM1 applies only to the current loop. Use the appropriate GM input stage for the particular loop calculations. Second, there are three battery conditions to consider. For the current loop, the battery is present and uncharged. Thus, the battery is modeled as a very large capacitance (greater than 1 Farad). For the voltage loop, the battery is -13-
ADP3810/ADP3811 VCS Input: ADP3810/ADP3811 VSENSE Input: ADP3810/ADP3811 Output Buffer: Optocoupler: Voltage Error Amplifier: Power Stage (General): Power Stage (Voltage Loop): Power Stage (Current Loop):
GM1 = 8.3 mA/V GM2 = 2.1 mA/V GM3 = 6 mA/V ITXoc = 0.36 mA/mA AV2 = VC/VX = 0.333 GM4 = V I C OMAX x RLOAD GM4 = 0.091 A/V GM4 = 1.0 A/V
IOMAX V OMAX
The gains for the ADP3810/ADP3811 GM amplifiers are based on typical measurements of the IC's open-loop gain, and they are expressed in units of milliamps per volt. The dc voltage gain REV. 0
ADP3810/ADP3811
either present or absent. If the battery is present, its large capacitance creates a very low frequency dominant pole, giving a single pole system. The more demanding case is when the battery is removed. Now the output pole is dependent upon the filter capacitors, CF1 and CF2. This pole is higher in frequency, and more care must be taken to stabilize the loop response. All three cases are described in detail below. The following calculations for compensation components help to realize stable voltage and current loops. In practical designs, checking the stability using a network analyzer or a Feedback Loop Analyzer is always recommended. The calculated component values serve as good starting values for a measurementbased optimization. The component values shown in Figure 23 are slightly different from the calculated values based on this optimization procedure. To simplify the analysis further, the loop gain is split into two components: the gain from the battery to the ADP3810/ ADP3811's COMP pin and the gain from the COMP pin back to the battery. Because the compensation of each loop depends upon the RC network on the COMP pin, it is a convenient choice for dividing the loop calculations.
Definitions: Step 2. Pick the voltage and current loop crossover frequencies, fCV and fCI:
To avoid interference between the voltage loop and the current loop, use fCV < 1/10 of fCI, the current loop crossover. The current loop crossover fCI is chosen to be ~ 1.9 kHz to provide a fast current limiting response time, so pick fCV ~ 100 Hz.
Step 3. Calculate GMOD at fCV:
The modulator gain of 46.7 dB is the dc gain. The modulator pole reduces this gain above fPM.
f GMOD (100 Hz ) = GMOD (dc)- 20 x log 1+ CV f PM
2 2
100 G MOD (100 Hz) = 48.3 dB - 20 x log 1+ = -10.9 dB 0.11
Step 4. Calculate gain loss of G EA at fCV:
To have the feedback loop gain cross over 0 dB at fCV = 100 Hz, GEA (100 Hz) should be +10.9 dB. Thus, the total gain loss of GEA needed at crossover is: GLOSS = GEA (dc) - GEA (100 Hz) = 48.5 dB - 10.9 dB = 37.6 dB
Step 5. Determine fP needed to achieve G LOSS:
Modulator Gain: GMOD = gain in dB from the COMP pin to VBAT. Error Amplifier: GEA = gain in dB from VBAT to the COMP pin. Loop Gain: GLOOP = GMOD + GEA. Modulator Pole: fPM, The pole present at the output of the modulator. Modulator Zero: fZM, The zero due to the ESR, RF1, of the filter cap, CF1.
Voltage Loop Compensation, No Battery Step 1. Calculate the dc loop gain (G LOOP), fPM, and fZM:
GMOD = 20 x log GM 3 x ITX OC x RF x AV 2 xGM 4 x R4
To achieve this GLOSS we need to add a pole, which is located at the COMP pin. GM2 has practically no parasitic loss in gain at 100 Hz. Its first parasitic pole occurs at approximately 500 kHz as shown in Figure 11. Thus, the entire gain loss must be realized with an external compensation capacitor, CC1, that sets the pole, fP1.
f P1 = f CV
GLOSS 10 10
= 1.3 Hz -1
[
]
Step 6. Calculate CC1 based upon fP:
CC1 = 1 0.3 F 2 x R5 x f P1
M:
6 mA / V x 0.36 x 3.3 k x GMOD = 20 x log = 48.3 dB 0.333 x 0.091 A / V x 1.2 k
Step 7. Calculate the loop phase margin,
G EA R2 = 20 x log xGM 2 x R5 R1+ R2
The loop phase margin is a combination of the phase of the modulator pole and zero and the error amplifier pole.
f f f M = 180 - arc tan CV - arc tan CV + arc tan CV 0 f P1 f PM f ZM
20 k G EA = 20 x log x 2.1mA /V x 400 k = 48.5 dB 80 k + 20 k
GLOOP = 44.5 dB + 48.3 dB = 96.8 dB
f PM = 1 1 = = 0.11 Hz 2 x R4 x (C F1 + C F2 ) 2 x1.2 k x (1.22 mF )
Step 8. Calculate RC1 to stabilize the loop:
f ZM =
1 1 = = 1.6 kHz 2 x RF1 x C F1 2 x 0.1 x 1.0 mF
The sum of phase losses of the modulator and error amplifier results in a loop phase of 0, which is unacceptable for loop stability. To stabilize the feedback loop, we have to add a phase boosting zero to the error amplifier by inserting a resistor (RC1) in series with the capacitor CC1. If the desired phase margin is M = 60 degrees, the frequency of the zero can be calculated: fZ1 = fCV/tan M = 57 Hz From this, the RC1 resistor is calculated:
RC1 = 1 10 k 2 x f Z1 x CC1
In reality, the interaction of CF1 and CF2 and their ESRs create an additional pole/zero pair, but because the value of RF1 (ESR of CF1) and RF2 (ESR of CF2) are similar, they tend to cancel each other out. Furthermore, the loop crossover is an order of magnitude lower in frequency, so the additional pole and zero have little effect on the loop response.
-14-
REV. 0
ADP3810/ADP3811
Step 9. Iterate CC1: Current Loop Compensation
Because fZ1 is very close to fCV, it will increase the error amplifier gain in a nonnegligible amount at the 0 dB point. The increase in gain is calculated as:
f 20 x log 1+ Z1 = 7.1dB f CV
2
Now that the voltage loop compensation is complete, it is time to add the compensation for the current loop. The definitions for modulator gain and error amplifier gain are the same as before; but now, the controlling error amplifier is GM1 in Figure 31, as opposed to GM2, for the voltage loop. Otherwise, the calculations are very similar.
Step 10. Calculate the dc loop gain (G LOOP), fPM, and fZM:
GMOD = 20 x log GM 3 x ITX OC x RF x AV 2 xGM 4 x RCS
6 mA /V x 0.36 x 3.3 k x G MOD = 20 x log = -4.5 dB 0.333 x1.0 A /V x 0.25
G EA = 20 x log GM1x R5 = 20 log
Now, the total error amplifier gain loss required is: GLOSS = 37.6 dB + 7.1 dB = 44.7 dB With this, the new fP1 can be calculated from the equation in Step 5. fP1 = 0.58 Hz Finally, CC1 is recalculated using the equation in Step 6.
CC1 = 1 0.7 F 2 x 400 k x 0.58 Hz
[
]
[ ] [8.3 mA /V x 400 k] = 70.4 dB
GLOOP = -6.1 dB + 70.4 dB = 64.3 dB
f PM = 1 1 = = 450 Hz 2 x ( RCS + RF1) x CF1 2 x 0.35 x1mF
Following these steps gives a cookbook method for calculating the compensation components for the voltage loop. As mentioned above, these components can be optimized in the actual circuit. The results of a PSpice1 analysis of the loop is shown in Figure 32. The open loop gain of the loop is 108 dB as calculated. The crossover frequency is 100 Hz with a phase margin of 52. The graph shows the phase leveling off at 90. In reality the phase will continue to fall as higher frequency parasitic poles take effect.
1
f ZM =
1 1 = =1.6 kHz 2 x RF1 x CF1 2 x 0.1 x1mF
Step 11. Pick the current loop crossover frequency, f CI:
From Step 2 in the voltage loop calculations, fCI ~ 1.9 kHz.
Step 12. Calculate GMOD at fCI:
PSpice is a trademark of MicroSim Corporation.
180
PHASE - Degrees
The modulator gain of -4.5 dB is the dc gain. The modulator pole reduces this gain above fPM.
f f G MOD = (1.9 kHz ) = G MOD (dc ) - 20 x log 1+ CI + 20 x log 1+ CI f PM f ZM
2 2
PHASE MARGIN = 52 90
0 200
GAIN - dB
100 0dB CROSSOVER 0 -100 0.01
If the 1 mF capacitor has a much higher ESR, e.g., 1 , the modulator zero, fZM, will be lower in frequency than the modulator pole, fPM. This causes the loop gain and bandwidth to increase and could cause instability. One possible solution to this scenario is to use a much higher value (47 nF) for the CF = 1 nF capacitor. The pole of this capacitor would then be in the 1 kHz range and would reduce the loop gain. If the ESR is much less than 0.1 , the bandwidth of the loop will decrease slightly.
100k
G MOD = (1.9 kHz ) = -4.5 dB -12.7 dB + 3.8 dB = -13.4 dB
0.1
1
10 100 FREQUENCY - Hz
1k
Step 13. Calculate gain loss of G EA at fCI:
Figure 32. Voltage Loop Gain/Phase Plots
Voltage Loop Compensation, Battery Present
When the battery has finished charging and is still connected to the charging circuitry, the system is said to be "floating" the battery. The loop is maintaining a constant output voltage equal to the battery voltage, and the output current has dropped to nearly zero. This case is actually the easiest to compensate because the battery's capacitance creates a very low frequency dominant pole, giving a single pole response. For example, if the battery is modeled as a 10 Farad capacitor, the dominant pole will be 1/(2 x 1.2 k x 10 F) = 0.013 MHz. This very low frequency pole causes the system to cross over 0 dB at less than 10 Hz, giving a stable single pole system. The compensation components have little effect on this response, so no further calculations are needed for this case. REV. 0
The gain loss of GEA in the current loop is a combination of the loss due to CC1, RC1 and the additional loss from CC2, RC2. To calculate the contribution of gain roll-off needed from CC2, RC2, the effective gain of GEA must first be calculated. Since the gain is calculated at 1.9 kHz, the impedance of CC1 is 120 . Thus, the gain becomes:
G EA (1.9 kHz ) = 20 x log GM1x ( R6 + RC1 +120 )
G EA (1.9 kHz ) = 20 x log 8.3 mA /V x (10320 ) = 38.9 dB
[
[
]
]
GLOSS = GEA (1.9 kHz) - GMOD (1.9 kHz) = 38.9 dB - 13.4 dB = 25.5 dB
-15-
ADP3810/ADP3811
Step 14. Calculate value of R C2 to realize GLOSS:
Assuming that CC2 is a short, RC2 forms a resistor divider with R3, reducing the loop gain. To calculate RC2, simply set the resistor ratio to give an attenuation of 25.5 dB, which is a loss of 1/20.
RC2 = R3 = 1k 20 -1
To provide some margin in the circuit for gain fluctuations in the various stages, the final value of RC2 was adjusted down to 300 .
Step 15. Calculate the value of C C2:
f Z3 =
1 = 78 Hz 2 x CC1 x ( RC1 + R6 )
To maintain high dc gain, a capacitor, CC2, is connected in series with RC2. The zero provided by this RC network should be close to fCI to provide a phase boost at crossover:
f Z 2 1.9 kHz
The final phase margin of 115 is more than adequate for a stable current loop. In reality, higher order parasitic poles reduce the phase margin to significantly less than 115 for a 1.9 kHz crossover. The same was not the case for the voltage loop because the cross over frequency of 100 Hz was well below the parasitic poles. A PSpice analysis of the resulting loop gain and phase for the values calculated is shown in Figure 33.
180
CC2 =
1 2 x f Z2 x RC2
=
1 200 nF 2 x1.9 kHz x 300
PHASE - Degrees
The pole frequency due to CC2 and R3 can now be calculated as:
1 f P2 = = 40 Hz 2 x CC2 x R3
PHASE MARGIN = 105 100
Step 16. Check the current loop phase margin:
f f f M = 180 - arc tan CI + arc tan CI - arc tan CI f P2 f Z2 f PM f CI f CI f CI +arc tan + arc tan f + arc tan f f ZM P1 Z3
0 100
GAIN - dB
50 0dB CROSSOVER 0 -50 0.01
M 115
0.1
1
10 100 FREQUENCY - Hz
1k
10k
100k
Figure 33. Current Loop Gain/Phase Plots
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Small Outline IC (SO-8)
0.1968 (5.00) 0.1890 (4.80)
8 1 5 4
0.1574 (4.00) 0.1497 (3.80)
0.2440 (6.20) 0.2284 (5.80)
PIN 1 0.0098 (0.25) 0.0040 (0.10)
0.0688 (1.75) 0.0532 (1.35)
0.0196 (0.50) x 45 0.0099 (0.25)
SEATING PLANE
0.0500 0.0192 (0.49) (1.27) 0.0138 (0.35) BSC
0.0098 (0.25) 0.0075 (0.19)
8 0
0.0500 (1.27) 0.0160 (0.41)
-16-
REV. 0
PRINTED IN U.S.A.
C2203-12-10/96
The above formula subtracts the phase of each pole and adds the phase of each zero. The poles and zeros come in pairs, fP2/fZ2 calculated in Step 15 from CC2/RC2; fPM/fZM calculated in Step 10 due to the output filter cap; and fP1/fZ3 due to CC1/RC1. fP1 is the same pole that was calculated in Step 9, and fZ3 needs to be recalculated with the addition of the internal 200 resistor as follows:

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